1. Field
One or more embodiments of the present invention relate to a method of manufacturing a semiconductor package substrate and a semiconductor package substrate manufactured using the method, and more particularly, to a method of manufacturing a semiconductor package substrate which has a simplified process and an upper and lower pattern alignment problem is solved, and a semiconductor package substrate manufactured using the method.
2. Description of the Related Art
A semiconductor device is used by being packaged in a semiconductor package substrate. The semiconductor package substrate in which the semiconductor device is packaged has a fine circuit pattern and/or I/O terminals. As high performance and/or high integration of a semiconductor device and miniaturization and/or high performance of an electronic device using the semiconductor device using the semiconductor device are being pursued, a fine circuit pattern of a semiconductor package substrate has a thinner line width and a higher complexity than circuit patterns in semiconductor package substrates related in the art.
In manufacturing a semiconductor package substrate of a related art, a through-hole is formed using a copper clad laminate (CCL) of accumulated copper foils and an inner surface of the through-hole is plated so that an upper surface copper foil and a lower surface copper foil are electrically connected. Then, the upper surface copper foil and the lower surface copper foil are patterned using photoresist, thereby manufacturing a semiconductor package substrate. However, according to the semiconductor package substrate manufacturing method of the related art, a manufacturing process becomes complicated and precision is lowered.